Nanoelectronic MOSFET (CMOS) circuits and physical level design

The book contains very relevant information on the features of modern SBIS technologies, the level of 130-90 Nm, which you need to know and take into account when designing. This information is set out in the first section (chapters 1-3) The second section (chapters 4-9) describes the corresponding design techniques for the physical level for mixed signal schemes and analog components, memory circuits, methods of reducing power consumption, input/output and protection from electrostatic discharge, signal integrity, taking into account long intercharits. In the third section (chapters 10-11), design techniques are considered, ensuring an increase in the output of suitable and taking into account variations of the technological process