Logical design and verification of systems on SystemVerilog
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The book is dedicated to SystemVerilog - the language of description of the equipment used to model electronic systems. SystemVerilog developers made it syntax similar to the syntax of the language C, which simplifies its development. In modern approaches to the design of the equipment, the modeling of the model (verification) is no less important than its development. SystemVerilog offers structures that allow better reflecting the engineering plan in models, software abstractions that simplify the development of test circles, statements that ensure verification of complex system behavior, as well as functional measuring instruments during verification.
The description of the language is given along with the material on logical design, so that the book can be used as a training manual for digital circuit and computers architecture courses.
The publication will be useful to students undergoing an introductory course of digital circuitry, as well as developers who are familiar with Verilog or VHDL, but want to refresh their skills or need a brief directory for SystemVerilog.
It is assumed that the reader has basic training in the field of circuitry and programming
The description of the language is given along with the material on logical design, so that the book can be used as a training manual for digital circuit and computers architecture courses.
The publication will be useful to students undergoing an introductory course of digital circuitry, as well as developers who are familiar with Verilog or VHDL, but want to refresh their skills or need a brief directory for SystemVerilog.
It is assumed that the reader has basic training in the field of circuitry and programming
Author:
Author:Donald Thomas
Cover:
Cover:Soft
Category:
- Category:Computer & Technology
ISBN:
ISBN:978-5-97060-619-3
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